> For the complete documentation index, see [llms.txt](https://fidesinnova.gitbook.io/docs/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://fidesinnova.gitbook.io/docs/fides-zero-knowledge-proof-zkp-algorithm/5-target-architecture.md).

# 5-target-architecture

- [Target architecture - RISC-V RV32IM](https://fidesinnova.gitbook.io/docs/fides-zero-knowledge-proof-zkp-algorithm/5-target-architecture/5-1-target-architecture-risc-v-rv32im.md): This phase requires a specific CPU architecture. In this page, we consider registers and instructions based on RISC-V RV32IM architecture.
- [Target architecture - ARMv6-M Cortex-M0 32-bit ARM - RaspberryPi Pico](https://fidesinnova.gitbook.io/docs/fides-zero-knowledge-proof-zkp-algorithm/5-target-architecture/5-2-target-architecture-armv6-m-cortex-m0-32-bit-arm-raspberrypi-pico.md): This phase requires a specific CPU architecture. In this page, we consider registers and instructions based on ARMv6-M Cortex-M0 32-bit ARM - RaspberryPi Pico
- [Target architecture - Cortex-A53 - for Siemens SIMATIC IOT2050](https://fidesinnova.gitbook.io/docs/fides-zero-knowledge-proof-zkp-algorithm/5-target-architecture/5-3-target-architecture-cortex-a53-for-siemens-simatic-iot2050.md): This phase requires a specific CPU architecture. In this page, we consider registers and instructions based on Cortex-A53 architecture.


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